Title :
Cascaded Time Difference Amplifier using Differential Logic Delay Cell
Author :
Mandai, Shingo ; Nakura, Toru ; Ikeda, Makoto ; Asada, Kunihiro
Author_Institution :
Dept. of Electr. Eng. & Inf. Syst., Univ. of Tokyo, Tokyo, Japan
Abstract :
We introduce a 42× cascaded time difference amplifier (TDA) using differential logic delay cells with 0.18 ¿m CMOS process. By employing differential logic cells for the delay chain instead of CMOS logic cells, our TDA has stable time difference gain (TD gain) and fine time resolution. Measurement results show that our TDA achieves less than 5.5% TD gain offset and ± 250 ps input range. Also the charge pump current of PMOS and NMOS unbalance can adjust the TD gain.
Keywords :
CMOS logic circuits; cascade networks; delay circuits; differential amplifiers; logic arrays; CMOS process; cascaded time difference amplifier; charge pump current; differential logic delay cell; size 0.18 mum; time difference gain; time resolution; CMOS logic circuits; Delay effects; Differential amplifiers; Gain control; Information systems; Inverters; Propagation delay; Signal resolution; Switches; Very large scale integration;
Conference_Titel :
SoC Design Conference (ISOCC), 2009 International
Conference_Location :
Busan
Print_ISBN :
978-1-4244-5034-3
Electronic_ISBN :
978-1-4244-5035-0
DOI :
10.1109/SOCDC.2009.5423907
