DocumentCode :
1647064
Title :
An SoC platform with on-chip web interface for in-field monitoring
Author :
Iizuka, Tetsuya ; Nakamura, Daisuke ; Yoshida, Hiroaki ; Komatsu, Satoshi ; Sasaki, Masahiro ; Ikeda, Makoto ; Asada, Kunihiro
Author_Institution :
VLSI Design & Educ. Center (VDEC), Univ. of Tokyo, Tokyo, Japan
fYear :
2009
Firstpage :
208
Lastpage :
211
Abstract :
As the VLSI technologies scale down to the nanometer regime, the circuit design and verification processes have become more and more complex and a reliable operation of VLSI becomes sensitive to the PVT (process, voltage, and temperature) variations. Therefore, the LSI test only before the shipment to screen out the initial failures has been insufficient to ensure the reliable in-field operation of LSI. In this paper, we propose an SoC platform with on-chip web interface to realize an in-field LSI testing and an easy access to the on-chip LSI monitoring circuits such as scan registers, temperature sensors, and so on. We can control the on-chip monitoring systems through the Web interface, and can monitor the LSI correct operations from remote locations using the proposed platform. Therefore, the proposed SoC platform realizes the LSI functionality monitoring even after the shipment and can test the in-field operation of LSI. This platform consists of 16-bit CPU, 64 K words of instruction/data memory, and 10Base-T Ethernet interface. A preliminary version of the proposed platform was implemented on 0.18 ¿m standard CMOS process. The area overhead is 8.44 mm2 on 0.18 ¿m process, and is estimated to scale down to about 1 mm2 on 65 nm process.
Keywords :
CMOS integrated circuits; Internet; VLSI; computerised monitoring; integrated circuit design; integrated circuit testing; large scale integration; network interfaces; system-on-chip; 10Base-T Ethernet interface; LSI functionality monitoring; SoC platform; VLSI technologies; circuit design; data memory; in-field LSI testing; in-field monitoring; on-chip LSI monitoring circuits; on-chip Web interface; scan registers; size 0.18 mum; size 65 nm; standard CMOS process; temperature sensors; verification process; Circuit synthesis; Circuit testing; Condition monitoring; Control systems; Large scale integration; Registers; Remote monitoring; Temperature sensors; Very large scale integration; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
SoC Design Conference (ISOCC), 2009 International
Conference_Location :
Busan
Print_ISBN :
978-1-4244-5034-3
Electronic_ISBN :
978-1-4244-5035-0
Type :
conf
DOI :
10.1109/SOCDC.2009.5423911
Filename :
5423911
Link To Document :
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