Methodology for Simultaneous Noise and Impedance Matching in W-Band LNAs

Author

Nicolson, S.T., Sr. ; Voinigescu, S.P., Sr.

Author_Institution

Edward S. Rogers, Sr. Dept. of Electr. & Comput. Eng., Toronto Univ., Ont.

fYear

2006

Firstpage

279

Lastpage

282

Abstract

This paper presents a step-by-step methodology for simultaneous noise and input impedance matching in CMOS and SiGe W-band LNAs. This technique yields either increased gain or reduced power dissipation. Additionally, techniques to determine the optimum layout for MOSFETs in mm-wave LNAs are discussed. Measurement results in 90nm CMOS show a 1-stage 1.8V, 78GHz LNA with 3.8dB gain and 16mW power dissipation, and a 1.8V, 2-stage 94GHz LNA with 4.8dB gain, and 30mW power dissipation. In all cases S₁₁ and S₂₂ are lower than -10 dB

Keywords

CMOS integrated circuits; Ge-Si alloys; MOSFET; circuit noise; impedance matching; low noise amplifiers; millimetre wave amplifiers; wideband amplifiers; 1.8 V; 16 mW; 3.8 dB; 30 mW; 4.8 dB; 78 GHz; 90 nm; 94 GHz; CMOS process; MOSFET; SiGe; SiGe W-band LNA; impedance matching; low noise amplifiers; mm-wave LNA; noise matching; power dissipation; wideband amplifiers; Bonding; Capacitance; Current density; Germanium silicon alloys; Impedance matching; Integrated circuit noise; MOSFETs; Power dissipation; Radio frequency; Silicon germanium; LNAs; Millimeter-wave circuits; W-band; noise matching; radio frequency CMOS;

fLanguage

English

Publisher

ieee

Conference_Titel

Compound Semiconductor Integrated Circuit Symposium, 2006. CSIC 2006. IEEE

Conference_Location

San Antonio, TX

Print_ISBN

1-4244-0126-7

Electronic_ISBN

1-4244-0127-5

Type

conf

DOI

10.1109/CSICS.2006.319954

Filename

4110041