Synchronous pipelined two-stage radix-4 200Mbps MB-OFDM UWB Viterbi decoder on FPGA

This paper proposes novel techniques for the synchronous pipelined two-stage radix-4 Viterbi decoder for 200 Mbps MB-OFDM UWB on FPGA. MB-OFDM UWB requires rate-1/3, 64-state Viterbi decoder to be implemented with 200 Mbps data rate and low power. To obtain low power, traceback method is used instead of register exchange method and to obtain high speed, radix-4 Viterbi decoder with two stages is used. Previous paper implemented two-stage, radix-4 Viterbi decoder on ASIC uses 3 pointer algorithm for decoding. In this paper, 2-pointer algorithm which reduces memory requirement compared to 3 pointer algorithm is implemented on FPGA. Also pipelining and LPM modules from ALTERA FPGA are used to achieve more speed. The proposed approach is implemented on ALTERA STRATIX III EP3SE80F1152C2 device and the speed achieved is 68.56 MHz with the throughput rate of 274 Mbps. In ASIC the module can be operated three times faster than FPGA.