A 5.15-5.825GHz CMOS Down-Conversion Mixer for WLAN 802.11a

This paper describes a 5.15GHz 5.825GHz CMOS down-conversion mixer for WLAN 802.11a receiver. Current reuse technique is adopted at the transconductance stage, and the folded topology with current bleeding is implemented at the switching stage. Since the transconductance stage and the switching stage are AC-coupled through capacitors, the DC bias is independently configured by this kind of topology. This mixer is implemented in IBM 0.13μm CMOS process, and the active chip area is 967μm×828μm. Operating from a 1.3V power supply, power consumption for this down-conversion mixer is 12mW. When 5.2GHz testing RF input is supplied, the measurement results show that the circuit achieves 10.5dB conversion gain, 14dBm input-referred third-order intercept point. The single-sideband noise figure is about 16.02dB.