• DocumentCode
    1647614
  • Title

    Easily Testable Implementation for Bit Parallel Multipliers in GF (2m)

  • Author

    Rahaman, H. ; Mathew, J. ; Jabir, A.M. ; Pradhan, D.K.

  • Author_Institution
    Dept. of Comput. Sci., Bristol Univ.
  • fYear
    2006
  • Firstpage
    48
  • Lastpage
    54
  • Abstract
    A testable implementation of bit parallel multiplier over the finite field GF(2m) is proposed. A function independent test set of length (2m+4), which detects all the single stuck-at faults in an m bit GF(2m) multiplier circuit, is also presented. Test set can be determined readily from the corresponding algebraic forms without running an ATPG tool. The test complexity is lower than ATPG generated or algorithmic test set. The test set provides 100 percent single stuck-at fault coverage. The gate counts of the proposed testable multiplier as a function of degree m has been analyzed. The testable circuit realization requires only two extra inputs for controllability and some additional EX ns and need field testing, built-in self-test (BIST) circuit may be used to generate test pattern internally for detecting faults in the multiplier circuits
  • Keywords
    automatic test pattern generation; controllability; design for testability; fault diagnosis; logic gates; logic testing; EXOR gate; algorithmic test set; bit parallel multiplier testable implementation; built-in self-test circuit; controllability; finite field; function independent test; stuck-at fault coverage; stuck-at fault detection; test complexity; test pattern generation; testability enhancement; testable circuit; testable multiplier circuit; Automatic test pattern generation; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Controllability; Electrical fault detection; Fault detection; Galois fields; Test pattern generators; Built-in Self-Test (BIST); Finite or Galois field; Mastrovito multiplier; cryptography; error control code; stuck-at fault;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    High-Level Design Validation and Test Workshop, 2006. Eleventh Annual IEEE International
  • Conference_Location
    Monterey, CA
  • ISSN
    1552-6674
  • Print_ISBN
    1-4244-0679-X
  • Electronic_ISBN
    1552-6674
  • Type

    conf

  • DOI
    10.1109/HLDVT.2006.320004
  • Filename
    4110061