Title :
FPGA-based single precision iterative floating point multiplier for educational use
Author :
Opritoiu, Flavius ; Carapencea, Sabina ; Vladutiu, Mircea
Author_Institution :
Comput. Sci. & Eng. Dept., Politeh. Univ. of Timisoara, Timisoara, Romania
Abstract :
An iterative, single precision, floating point multiplier is described in this paper, designed and verified using the Verilog description language. The design is provided for educational use, complementing the practical activity in Computer Architecture related courses. The area overhead of the architecture is reduced by resorting to shift-and-add multiplication, allowing to conveniently storing the mantissa result on the required number of bits while facilitating the management of the rounding bits. The architecture was designed as a case study for different adder configuration as well as various sequential binary multiplication procedures.
Keywords :
field programmable gate arrays; floating point arithmetic; hardware description languages; iterative methods; logic design; FPGA based single precision iterative floating point multiplier; Verilog description language; educational use; sequential binary multiplication procedures; shift and add multiplication; Adders; Algorithm design and analysis; Central Processing Unit; Computer architecture; Computers; Education; Field programmable gate arrays; Educational Design; Floating Point Multiplier; Iterative Implementation; Single Precision IEEE 754;
Conference_Titel :
Design and Technology in Electronic Packaging (SIITME), 2014 IEEE 20th International Symposium for
Conference_Location :
Bucharest
DOI :
10.1109/SIITME.2014.6967049
