Title :
Decoupled value prediction on trace processors
Author :
Lee, Sang-Jeong ; Wang, Yuan ; Yew, Pen-Chung
Author_Institution :
Dept. of Comput. Sci. & Eng., Soonchunhyang Univ., Chungnam, South Korea
fDate :
6/22/1905 12:00:00 AM
Abstract :
Value prediction is a technique that breaks true data dependences by predicting the outcome of an instruction, and executes speculatively its data-dependent instructions based on the predicted outcome. In this paper, we address several implementation issues for value prediction which are important on wide-issue superscalar architectures, and present a value prediction scheme based on the trace processor. The scheme decouples the value prediction from the instruction fetch stage and uses a hybrid predictor with dynamic classification. We use execution-driven simulation to study the performance of such a scheme using SPECint95 benchmarks
Keywords :
parallel architectures; performance evaluation; dynamic classification; execution-driven simulation; hybrid predictor; instruction fetch stage; performance; superscalar architectures; trace processor; trace processors; value prediction; Clocks; Computer science; Decoding; Electronic switching systems; Hardware; Parallel processing; Performance gain; Registers;
Conference_Titel :
High-Performance Computer Architecture, 2000. HPCA-6. Proceedings. Sixth International Symposium on
Conference_Location :
Touluse
Print_ISBN :
0-7695-0550-3
DOI :
10.1109/HPCA.2000.824353