• DocumentCode
    1647682
  • Title

    Error Detection Using Model Checking vs. Simulation

  • Author

    Verma, Shireesh ; Lee, Patricia ; Harris, Ian G.

  • Author_Institution
    Dept. of Comput. Sci., California Univ., Irvine, CA
  • fYear
    2006
  • Firstpage
    55
  • Lastpage
    58
  • Abstract
    Design simulation and model checking are two alternative and complementary techniques for verifying hardware designs. This paper presents a comparison between the two techniques based on detection of design errors, performance, and memory use. We perform error detection experiments using model checking and simulation to detect errors injected into a verification benchmark suite. The results allow a quantitative comparison of simulation and model checking which can be used to understand weaknesses of both approaches
  • Keywords
    design for testability; error detection; formal verification; virtual machines; design error detection experiment; design simulation; hardware design verification; memory use; model checking; verification benchmark suite; Automata; Computational modeling; Computer errors; Computer science; Computer simulation; Conferences; Hardware; Testing; USA Councils; Vehicles;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    High-Level Design Validation and Test Workshop, 2006. Eleventh Annual IEEE International
  • Conference_Location
    Monterey, CA
  • ISSN
    1552-6674
  • Print_ISBN
    1-4244-0680-3
  • Electronic_ISBN
    1552-6674
  • Type

    conf

  • DOI
    10.1109/HLDVT.2006.319964
  • Filename
    4110063