Title :
Dynamic noise margins of MOS logic gates
Author :
Zurada, Jacek M. ; Joo, Yu Sang ; Bell, Samuel V.
Author_Institution :
Dept. of Electr. Eng., Louisville Univ., KY, USA
Abstract :
Voltage transfer characteristics and static noise margins of basic NMOS and CMOS inverter connections are reviewed in terms of their logic dynamic performances and dynamic noise margins. The hysteresis phenomena, immunity to short pulse inputs, and noise margins depending upon both the capacitive load and the speed of the input signal are presented and discussed. The results of this study contribute to an understanding of the switching phenomena of VLSI logic and to the determining of the dynamic characteristics, including noise immunity, from well-understood static performance
Keywords :
CMOS integrated circuits; MOS integrated circuits; electron device noise; integrated logic circuits; logic gates; CMOS; MOS logic gates; NMOS; capacitive load; dynamic noise margins; hysteresis phenomena; input signal; inverter connections; logic dynamic performances; noise immunity; short pulse inputs; static noise margins; switching phenomena; CMOS logic circuits; Hysteresis; Inverters; Logic gates; MOS devices; Shape; Switching circuits; Transient analysis; Very large scale integration; Voltage;
Conference_Titel :
Circuits and Systems, 1989., IEEE International Symposium on
Conference_Location :
Portland, OR
DOI :
10.1109/ISCAS.1989.100557
