Title :
EXPAC: a parameter extractor and electrical verifier for VLSI ICs
Author :
Serrano, J.P. ; Lopez, J.C. ; Santos, Aldri
Author_Institution :
E.T.S.I. Telecomunicacion, Univ. Politecnica de Madrid, Spain
Abstract :
A parameter extractor for VLSI circuits that obtains the electrical description from the layout geometry is described. The extractor includes an electrical-to-electrical comparator to verify the circuit by matching the components with a user-supplied description. It can be customized to any NOS or CMOS technology using a technological file. The basic algorithm is described, and the results obtained for several circuits are discussed
Keywords :
VLSI; circuit CAD; integrated circuit technology; CAD; CMOS; EXPAC; NOS; VLSI ICs; electrical description; electrical verifier; layout geometry; parameter extractor; technological file; CMOS technology; Capacitors; Circuit analysis; Circuit simulation; Data mining; Geometry; Integrated circuit layout; MOS devices; SPICE; Very large scale integration;
Conference_Titel :
Electrotechnical Conference, 1991. Proceedings., 6th Mediterranean
Conference_Location :
LJubljana
Print_ISBN :
0-87942-655-1
DOI :
10.1109/MELCON.1991.161824
