A globally asynchronous locally synchronous DMR architecture for aggressive low-power fault toleration

Recently, dual or triple modular redundancy (DMR/TMR) has been commonly used in high-end server or special environment targeted microprocessors to mitigate single event effects (SEEs), as the miniaturized transistors tend to be more vulnerable to SEEs. However, facing the issue that DMR and TMR usually add remarkable pressures to the power consumption due to the highly redundant executions, this work specially provides an architectural solution to introduce aggressive dynamic voltage scaling (DVS) and Razor-FF on DMR architecture to moderate the total energy. As the traditional DMR architecture with a globally synchronous clock will have visible performance down-gradation when DVS and Razor-FF are used, in this work, we propose a DMR processor architecture that uses dedicated clocks on each DMR module, following a globally asynchronous locally synchronous (GALS) execution fashion. In the execution, due to the possible timing faults from the aggressively lowered voltage, the two modules may experience a dynamically phase-shift clock frequency. Our GALS DMR approach is assembled with FIFOs and delay buffers to conceal the effect from this phase-shift and thereby the performance impact is largely alleviated. Compared to the traditional synchronous DMR system, we can have around 10% performance improvement by this asynchronous scheme when a same power reduction ratio is assumed. Also, we have aggressively turned down the voltage and achieved a 12% better MIPS/W than the previous DMR without major performance influence.