An area and time efficient collapsed modified CORDIC DDFS architecture for high rate digital receivers

This paper presents a novel technique for DDFS based on proposed collapsed modified CORDIC algorithm. The design based on this technique is highly area and power efficient and is capable of computing cosine and sine values in a single cycle at high clock rate. The design presented in this paper is part of a high rate communication system and is mapped on Xilinx Virtex 2 series FPGA XC2V6000. It synthesized at 100 MHz without any pipelining and 175 MHz with single stage pipeline.