DocumentCode
1648295
Title
Runtime Deadlock Analysis of SystemC Designs
Author
Cheung, Eric ; Satapathy, Piyush ; Pham, Vi ; Hsieh, Harry ; Chen, Xi
Author_Institution
Dept. of Comput. Sci., Univ. of California Riverside, CA
fYear
2006
Firstpage
187
Lastpage
194
Abstract
SystemC has gained popularity as a modeling language in the design of highly complex, heterogeneous, and large concurrent systems. Efficient and accurate simulation of the SystemC designs has become increasingly important. In this paper, we analyze the synchronization dependencies of concurrent systems modeled in the SystemC environment, where SystemC models are simulated through a discrete event simulation kernel that schedules events at runtime. We discuss different possibilities of SystemC communication constructs that may lead to deadlocks. We create a framework for system level designers to detect the deadlocks as soon as they occur, thus avoiding more complicated scenarios later in the simulation. This is accomplished by extension of the SystemC simulation kernel to build a dynamic dependency graph incrementally at runtime, and then applying an incremental deadlock detection algorithm to the graph. We demonstrate our approach through the well established dining philosopher problem and two real world designs, CS6100 JPEG encoder and MPEG-2 decoder. The overhead on the overall simulation is shown to be insignificant
Keywords
concurrency control; discrete event simulation; graph theory; processor scheduling; specification languages; synchronisation; systems analysis; SystemC communication constructs; SystemC designs; SystemC simulation kernel; concurrent systems; discrete event simulation kernel; incremental deadlock detection; incremental dynamic dependency graph building; modeling language; runtime deadlock analysis; runtime event scheduling; synchronization dependencies; system level design; Computational modeling; Design methodology; Discrete event simulation; Hardware; Kernel; Runtime; Software performance; System recovery; System-level design; USA Councils; SystemC; Verification; cyclic dependency; deadlock; simulation; synchronization; system level design;
fLanguage
English
Publisher
ieee
Conference_Titel
High-Level Design Validation and Test Workshop, 2006. Eleventh Annual IEEE International
Conference_Location
Monterey, CA
ISSN
1552-6674
Print_ISBN
1-4244-0679-X
Electronic_ISBN
1552-6674
Type
conf
DOI
10.1109/HLDVT.2006.319990
Filename
4110089
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