Reliability improvement in planar MONOS cell for 20nm-node multi-level NAND Flash memory and beyond

Author

Sakamoto, Wataru ; Yaegashi, Toshitake ; Okamura, Takayuki ; Toba, Takayuki ; Komiya, Ken ; Sakuma, Kiwamu ; Matsunaga, Yasuhiko ; Ishibashi, Yutaka ; Nagashima, Hidenobu ; Sugi, Motoki ; Kawada, Nobuhito ; Umemura, Masashi ; Kondo, Masaki ; Izumida, Taka

Author_Institution

Center for Semicond. R&D, Toshiba Corp., Yokohama, Japan

fYear

2009

Firstpage

1

Lastpage

4

Abstract

20 nm-node planar MONOS cell which has improved reliability is developed. Extremely wide program/erase Vth window and good retention characteristics after cycling stress are obtained by buried charge cell structure. Moreover, Vth shift by interference between adjacent cells has smaller dependence on the cell-cell space than Vth window improvement when the half pitch is constant. These results show that the buried charge planar MONOS cell is suitable for Flash memory with 20 nm-node and beyond.

Keywords

NAND circuits; circuit reliability; flash memories; buried charge planar MONOS cell; cell-cell space; charge cell structure; cycling stress; multilevel NAND flash memory; program/erase Vth window; reliability improvement; retention characteristics; size 20 nm; Aluminum oxide; Interference; Laboratories; Large scale integration; MONOS devices; Manufacturing processes; Research and development; Semiconductor device reliability; Silicon compounds; Stress;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting (IEDM), 2009 IEEE International

Conference_Location

Baltimore, MD

Print_ISBN

978-1-4244-5639-0

Electronic_ISBN

978-1-4244-5640-6

Type

conf

DOI

10.1109/IEDM.2009.5424211

Filename

5424211