Efficient systolic array implementations of digital filtering

Four different realization schemes are proposed to improve hardware efficiency for the systolic array implementation of a general class of IIR digital filters that includes the classical direct-form digital filter, the Gray-Markel digital lattice or ladder filters, and the Rao-Kailath orthogonal digital filters. The four schemes use: (1) two interleaved-signal sequences; (2) two-module processing elements (PEs); (3) two overlapped cascaded smaller filters; and (4) a systolic ring. Each scheme has its own advantages and disadvantages. The first scheme can always achieve 100% hardware utilization, but it only applies to the digital filtering of two data sequences. The second scheme is simple and straightforward, but it needs more multiplexers than the other schemes. The third scheme needs only one multiplexer, but the transfer function has to be factorized. The fourth scheme also needs only one multiplexer, but it can have more half-active PEs in some cases. Which scheme is preferable depends on specific situations and applications. Generally speaking, all four of these proposed schemes can improve the hardware efficiency to (or near) 100% with low control overhead