• DocumentCode
    1649794
  • Title

    Design space and scalability exploration of 1T-1STT MTJ memory arrays in the presence of variability and disturbances

  • Author

    Raychowdhury, Arijit ; Somasekhar, Dinesh ; Karnik, Tanay ; De, Vivek

  • Author_Institution
    Circuits Res. Lab., Intel Corp., Hillsboro, OR, USA
  • fYear
    2009
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    This paper presents modeling and analysis of 1T-1MTJ STT RAM memory arrays under process variations and thermal disturbances. Bounds on the magnetic material design space for embedded applications are illustrated. Impact of relaxed timing/area and the effect of scaling for 1T-1MTJ bitcells have been evaluated.
  • Keywords
    integrated circuit design; integrated circuit reliability; logic arrays; random-access storage; 1T-1STT MTJ memory array; RAM memory arrays; design space exploration; embedded applications; magnetic material design space; process variations; scalability exploration; thermal disturbances; CMOS technology; Logic arrays; Magnetic materials; Magnetic tunneling; Random access memory; Read-write memory; Scalability; Space exploration; Space technology; Torque;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electron Devices Meeting (IEDM), 2009 IEEE International
  • Conference_Location
    Baltimore, MD
  • Print_ISBN
    978-1-4244-5639-0
  • Electronic_ISBN
    978-1-4244-5640-6
  • Type

    conf

  • DOI
    10.1109/IEDM.2009.5424242
  • Filename
    5424242
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1649794