Crypto processor for contactless smart cards

In this paper a crypto processor for contactless smart cards is presented. The proposed architecture is based on DES algorithm standard. The introduction in the proposed system a power management unit results in a significant power consumption reduction. The use of feedback design techniques reduces the required silicon area. The overall system throughput satisfies the contactless smart card data rate demands. The proposed system operates in 55 MHz frequency with maximum data rate 42.5 Mbps. A 50% power reduction, in comparison with conventional implementations, has estimated mainly due to the switching activity and the total memory accesses reduction. Additional techniques for silicon area reduction are also presented.