• DocumentCode
    1649965
  • Title

    Analysis and Modeling of CD Variation for Statistical Static Timing

  • Author

    Cline, Brian ; Chopra, Kaviraj ; Blaauw, David ; Cao, Yu

  • Author_Institution
    Michigan Univ., Ann Arbor, MI
  • fYear
    2006
  • Firstpage
    60
  • Lastpage
    66
  • Abstract
    Statistical static timing analysis (SSTA) has become a key method for analyzing the effect of process variation in aggressively scaled CMOS technologies. Much research has focused on the modeling of spatial correlation in SSTA. However, the vast majority of these works used artificially generated process data to test the proposed models. Hence, it is difficult to determine the actual effectiveness of these methods, the conditions under which they are necessary, and whether they lead to a significant increase in accuracy that warrants their increased runtime and complexity. In this paper, we study 5 different correlation models and their associated SSTA methods using 35420 critical dimension (CD) measurements that were extracted from 23 reticles on 5 wafers in a 130nm CMOS process. Based on the measured CD data, we analyze the correlation as a function of distance and generate 5 distinct correlation models, ranging from simple models which incorporate one or two variation components to more complex models that utilize principle component analysis and quad-trees. We then study the accuracy of the different models and compare their SSTA results with the result of running STA directly on the extracted data. We also examine the trade-off between model accuracy and run time, as well as the impact of die size on model accuracy. We show that, especially for small dies (6.6mm times 5.7mm), the simple models provide comparable accuracy to that of the more complex ones, while incurring significantly less runtime and implementation difficulty. The results of this study demonstrate that correlation models for SSTA must be carefully tested on actual process data and must be used judiciously
  • Keywords
    delay circuits; principal component analysis; timing circuits; correlation model; critical dimension data; critical dimension measurement; critical dimension variation; principle component analysis; quad-trees; statistical static timing analysis; CMOS process; CMOS technology; Circuits; Delay; Principal component analysis; Random variables; Runtime; Semiconductor device modeling; Testing; Timing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer-Aided Design, 2006. ICCAD '06. IEEE/ACM International Conference on
  • Conference_Location
    San Jose, CA
  • ISSN
    1092-3152
  • Print_ISBN
    1-59593-389-1
  • Electronic_ISBN
    1092-3152
  • Type

    conf

  • DOI
    10.1109/ICCAD.2006.320134
  • Filename
    4110154