DocumentCode
1650150
Title
High performance 32nm logic technology featuring 2nd generation high-k + metal gate transistors
Author
Packan, P. ; Akbar, S. ; Armstrong, M. ; Bergstrom, D. ; Brazier, M. ; Deshpande, H. ; Dev, K. ; Ding, G. ; Ghani, T. ; Golonzka, O. ; Han, W. ; He, J. ; Heussner, R. ; James, R. ; Jopling, J. ; Kenyon, C. ; Lee, SH ; Liu, M. ; Lodha, S. ; Mattis, B. ; Mu
Author_Institution
Logic Technol. Dev., Intel Corp., Hillsboro, OR, USA
fYear
2009
Firstpage
1
Lastpage
4
Abstract
A 32 nm logic technology for high performance microprocessors is described. 2nd generation high-k + metal gate transistors provide record drive currents at the tightest gate pitch reported for any 32 nm or 28 nm logic technology. NMOS drive currents are 1.62 mA/um Idsat and 0.231 mA/um Idlin at 1.0 V and 100 nA/um Ioff. PMOS drive currents are 1.37 mA/um Idsat and 0.240 mA/um Idlin at 1.0 V and 100 nA/um Ioff. The impact of SRAM cell and array size on Vccmin is reported.
Keywords
MOS logic circuits; SRAM chips; NMOS drive current; PMOS drive current; SRAM cell; gate pitch; high-k transistors; logic technology; metal gate transistors; microprocessors; size 28 nm; size 32 nm; voltage 1.0 V; Capacitive sensors; Electronic mail; Helium; High K dielectric materials; High-K gate dielectrics; Logic; MOS devices; Moore´s Law; Reliability engineering; Silicon;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting (IEDM), 2009 IEEE International
Conference_Location
Baltimore, MD
Print_ISBN
978-1-4244-5639-0
Electronic_ISBN
978-1-4244-5640-6
Type
conf
DOI
10.1109/IEDM.2009.5424253
Filename
5424253
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