Title :
Competitive and cost effective high-k based 28nm CMOS technology for low power applications
Author :
Arnaud, F. ; Thean, A. ; Eller, M. ; Lipinski, M. ; Teh, Y.W. ; Ostermayr, M. ; Kang, K. ; Kim, N.S. ; Ohuchi, K. ; Han, J.-P. ; Nair, D.R. ; Lian, J. ; Uchimura, S. ; Kohler, S. ; Miyaki, S. ; Ferreira, P. ; Park, J.-H. ; Hamaguchi, M. ; Miyashita, K. ;
Author_Institution :
Semicond. R&D Center (SRDC), IBM Microelectron. Div., Hopewell Junction, NY, USA
Abstract :
In this paper, we present a cost-effective 28 nm CMOS technology for low power (LP) applications based on a high-k, single-metal-gate-first architecture. We report raw gate densities up to 4200 kGate/mm2, and, using the ARM Cortex-R4F as a reference, we report achievement of an overall 2.4x area reduction in 28 nm from 45 nm technology. Our high-density SRAM bit-cell (area= 0.120mm2) has a demonstrated Static Noise Margin (SNM) of 213 mV at 1 V. Fully compatible with power/leakage management techniques intensively used in low power designs, the transistor drive currents are increased +35% & +10%, for nFET and pFET respectively, with respect to a 28 nm LP poly/SiON reference. Compatible with LP system-on-chip requirements, ultra low-cost, high performance analog devices are reported which leverage a dramatic improvement in matching factor (AVT~2mV.um) versus our previously-reported result. An optimized interconnection scheme based on Extreme Low k (ELK) dielectric (k~2.4) and advanced metallization allows high density wiring with competitive R-C versus our previous technology.
Keywords :
CMOS integrated circuits; SRAM chips; field effect transistors; high-k dielectric thin films; integrated circuit interconnections; integrated circuit metallisation; low-power electronics; system-on-chip; ARM Cortex-R4F; LP poly-SiON reference; LP system-on-chip requirements; advanced metallization; cost effective high-k based CMOS technology; extreme low k dielectric; high density wiring; high performance analog devices; high-density SRAM bit-cell; leakage management techniques; low power designs; nFET; optimized interconnection scheme; pFET; power management techniques; single-metal-gate-first architecture; size 28 nm; size 45 nm; static noise margin; transistor drive currents; voltage 1 V; voltage 213 mV; CMOS technology; Costs; Energy management; High K dielectric materials; High-K gate dielectrics; Metallization; Power system management; Random access memory; System-on-a-chip; Wiring;
Conference_Titel :
Electron Devices Meeting (IEDM), 2009 IEEE International
Conference_Location :
Baltimore, MD
Print_ISBN :
978-1-4244-5639-0
Electronic_ISBN :
978-1-4244-5640-6
DOI :
10.1109/IEDM.2009.5424255
