Title :
A stacked SONOS technology, up to 4 levels and 6nm crystalline nanowires, with Gate-All-Around or independent gates (φ-Flash), suitable for full 3D integration
Author :
Hubert, A. ; Nowak, E. ; Tachi, K. ; Maffini-Alvaro, V. ; Vizioz, C. ; Arvet, C. ; Colonna, J.P. ; Hartmann, J.-M. ; Loup, V. ; Baud, L. ; Pauliac, S. ; Delaye, V. ; Carabasse, C. ; Molas, G. ; Ghibaudo, G. ; De Salvo, B. ; Faynot, O. ; Ernst, T.
Author_Institution :
CEA-LETI, MINATEC, Grenoble, France
Abstract :
We present the first experimental study of a Gate-All-Around (GAA) SONOS memory architecture with 4-level crystalline nanowire channels (down to 6 nm-diameter). The technology is also extended to an independent double gate memory architecture, called Φ-Flash. The experimental results with 6 nm nanowires show high programming windows (up to 7.4 V), making the structure compatible with multilevel operation. Excellent retention even after 104 cycles is achieved. The independent double gate option has otherwise been successfully integrated with 4-level stacked nanowires for multibit applications. The Φ-Flash exhibits up to 1.8 V ΔVTh between its two gates, demonstrating multibits operation. The basic process to fully disconnect the different nanowires in view of a full 3D integration of a memory array is discussed.
Keywords :
flash memories; logic gates; nanoelectronics; nanowires; semiconductor storage; semiconductor-insulator-semiconductor devices; Φ-Flash; 4-level crystalline nanowire channels; full 3D integration; gate-all-around SONOS memory architecture; independent double gate memory architecture; memory array; size 6 nm; stacked SONOS technology; Crystallization; Nanowires; SONOS devices;
Conference_Titel :
Electron Devices Meeting (IEDM), 2009 IEEE International
Conference_Location :
Baltimore, MD
Print_ISBN :
978-1-4244-5639-0
Electronic_ISBN :
978-1-4244-5640-6
DOI :
10.1109/IEDM.2009.5424260
