Engineering of strained III–V heterostructures for high hole mobility

Author

Nainani, Aneesh ; Raghunathan, Shyam ; Witte, Daniel ; Kobayashi, Masaharu ; Irisawa, Toshifumi ; Krishnamohan, Tejas ; Saraswat, Krishna ; Bennett, Brian R. ; Ancona, Mario G. ; Boos, J. Brad

Author_Institution

Center for Integrated Syst., Stanford Univ., Stanford, CA, USA

fYear

2009

Firstpage

1

Lastpage

4

Abstract

Strain and confinement leads to reduction in m* to numbers comparable with electron mass in III-V´s. Room temperature mobility of 960/860cm²/Vs for In_0.41Ga_0.59Sb/GaSb channels (N_S=1Ã—10¹²/cm²) are the highest reported for these materials. Â¿h is > 3X compared to uniaxially strained Si. Further enhancement should be possible using uniaxial strain (Fig. 3). High Â¿h Sb-based channels along with their already reported excellent n-channel performance make them promising candidates to meet ITRS requirements for future nodes.

Keywords

III-V semiconductors; hole mobility; semiconductor device models; ITRS requirements; confinement leads; electron mass; high hole mobility; n-channel performance; room temperature mobility; strained III-V heterostructures; temperature 293 K to 298 K; CMOS logic circuits; Capacitive sensors; III-V semiconductor materials; Lattices; Light scattering; Performance evaluation; Superlattices; Temperature dependence; Temperature measurement; X-ray scattering;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting (IEDM), 2009 IEEE International

Conference_Location

Baltimore, MD

Print_ISBN

978-1-4244-5639-0

Electronic_ISBN

978-1-4244-5640-6

Type

conf

DOI

10.1109/IEDM.2009.5424267

Filename

5424267