1650545

Interfacial layer dependence of HFSI_xO_y gate stacks on V_T instability and charge trapping using ultra-short pulse in characterization

Young, C.D. ; Choi, R. ; Sim, J.H. ; Lee, B.H. ; Zeitzoff, P. ; Zhao, Y. ; Matthews, K. ; Brown, G.A. ; Bersuker, G.

SEMATECH, Austin, TX, USA

2005

75

79

MOSFET; dielectric thin films; electron traps; hafnium compounds; semiconductor device measurement; 35 ns to 5 ms; DC characteristics degradation; HfSi_xO_x; charge trapping; charging bias dependence; electron trapping; fast transient charging times; gate stack interfacial layer dependence; high-k transistors; interfacial layer thickness; nMOS transistors; threshold voltage instability; trap-free pulse I-V characteristics; ultra-short pulse I-V characterization; Annealing; Degradation; Dielectrics; Electron traps; Oscilloscopes; Pulse generation; Pulse measurements; Pulse shaping methods; Space vector pulse width modulation; Voltage;

English

ieee

Reliability Physics Symposium, 2005. Proceedings. 43rd Annual. 2005 IEEE International

0-7803-8803-8

conf

10.1109/RELPHY.2005.1493066

1493066