Optimization of metallization processes for 32-nm-node highly reliable ultralow-k (k=2.4)/Cu multilevel interconnects incorporating a bilayer low-k barrier cap (k=3.9)

Author

Iguchi, M. ; Yokogawa, S. ; Aizawa, H. ; Kakuhara, Y. ; Tsuchiya, H. ; Okada, N. ; Imai, K. ; Tohara, M. ; Fujii, K. ; Watanabe, T.

Author_Institution

Adv. Device Dev. Div., NEC Electron. Corp., Sagamihara, Japan

fYear

2009

Firstpage

1

Lastpage

4

Abstract

Reliability of 32-nm-node ultralow-k (k=2.4)/Cu multilevel interconnects incorporating a bilayer low-k barrier cap (k=3.9) was improved without excessive wiring resistance by using CuAl seed technology with high-temperature and short-time annealing. Though the increase in wiring resistivity was about 10%, both electromigration (EM) and stress-induced voiding (SiV) reliability was clearly improved by using Cu-0.5 wt%Al seed metal.

Keywords

annealing; copper compounds; electromigration; low-k dielectric thin films; metallisation; Cu; CuAl; CuAl seed technology; bilayer low-k barrier cap; copper interconnect; electromigration; high-temperature annealing; metallization process; short-time annealing; size 32 nm; stress-induced voiding reliability; ultralow-k multilevel interconnects; Annealing; Conductivity; Copper; Electrical resistance measurement; Grain size; Integrated circuit interconnections; Metallization; National electric code; Semiconductor device reliability; Wiring;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting (IEDM), 2009 IEEE International

Conference_Location

Baltimore, MD

Print_ISBN

978-1-4244-5639-0

Electronic_ISBN

978-1-4244-5640-6

Type

conf

DOI

10.1109/IEDM.2009.5424270

Filename

5424270