Title :
Chip-level and package-level seamless interconnect technologies for advanced packaging
Author :
Yamamichi, Shintaro ; Mori, Kentaro ; Kikuchi, Katsumi ; Murai, Hideya ; Ohshima, Daisuke ; Nakashima, Yoshiki ; Soejima, Koji ; Kawano, Masaya ; Murakami, Tomoo
Author_Institution :
Device Platforms Res. Labs., NEC Corp., Sagamihara, Japan
Abstract :
Package-process-oriented thick-Cu-wiring technologies have been developed for forming chip-level and package-level seamless interconnects between an LSI chip and the package substrate. Chip-level seamless interconnects are formed using a resin CMP process. Package-level seamless interconnects are formed by embedding a thinned chip into a resin on Cu base plate. A package with package-level seamless interconnects is thinner and has lower thermal resistance, better power delivery, and finer-pitch interconnects than a conventional flip-chip ball grid array package.
Keywords :
chemical mechanical polishing; integrated circuit interconnections; integrated circuit metallisation; integrated circuit packaging; large scale integration; Cu; LSI chip; advanced packaging; chip level seamless interconnect technology; fine pitch interconnect; package level seamless interconnect technology; package process oriented thick copper wiring technology; package substrate; resin CMP process; thermal resistance; Bonding; Electronic packaging thermal management; Electronics packaging; Large scale integration; National electric code; Resins; Rough surfaces; Surface roughness; Wire; Wiring;
Conference_Titel :
Electron Devices Meeting (IEDM), 2009 IEEE International
Conference_Location :
Baltimore, MD
Print_ISBN :
978-1-4244-5639-0
Electronic_ISBN :
978-1-4244-5640-6
DOI :
10.1109/IEDM.2009.5424273
