Homogeneous VLSI for 2-D digital signal processing

A discussion is presented of the VLSI implementation of processing elements that can be used in very high-throughput two-dimensional signal processing systems. The architecture is based entirely on a single generic cell and forms naturally homogeneous architectures when used to implement bit-level systolic arrays over finite rings. The authors briefly discuss the cellular structure that is used to implement the bit-level arrays, introduce a novel circuit form that allows very fast processing for any CMOS technology, and, as an example, discuss the implementation of a two-dimensional computational element for high-throughput DFT processors. The VLSI array implementation for the DFT computational element is illustrated by a mask layout in a double-metal 3-μm CMOS technology; projected throughput rates in this technology are simulated in excess of 45 M samples/s