DocumentCode
1651036
Title
Integrated circuits using top-gate ZnO nanowire transistors with ultrathin organic gate dielectric
Author
Kälblein, D. ; Böttcher, H.J. ; Weitz, R.T. ; Zschieschang, U. ; Kern, K. ; Klauk, H.
Author_Institution
Max Planck Inst. for Solid State Res., Stuttgart, Germany
fYear
2009
Firstpage
1
Lastpage
4
Abstract
We report on field-effect transistors based on single-crystalline ZnO nanowires with a diameter of about 50 nm grown by wet-chemical synthesis. The as-grown nanowires have a large conductivity that makes it difficult to control the drain current with the gate field, but the conductivity is greatly reduced by a post-growth anneal at 600°C. Using a solution-processed organic gate dielectric with a thickness of 2.1 nm and overlapping metal top gate electrodes patterned by electron-beam lithography we have prepared nanowire transistors with good static performance. By patterning more than one transistor on the same nanowire we have also prepared simple logic circuits on a single nanowire.
Keywords
II-VI semiconductors; electron beam lithography; field effect transistors; integrated logic circuits; nanofabrication; nanowires; semiconductor growth; wide band gap semiconductors; zinc compounds; ZnO; electron-beam lithography; field-effect transistors; integrated circuits; logic circuits; overlapping metal top gate electrodes; post-growth annealling; single-crystalline ZnO nanowires; size 2.1 nm; solution-processed organic gate dielectric; temperature 600 degC; top-gate ZnO nanowire transistors; ultrathin organic gate dielectric; wet-chemical synthesis; Annealing; Conductivity; Dielectrics; FETs; Lithography; Scanning electron microscopy; Substrates; Temperature; Thin film transistors; Zinc oxide;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting (IEDM), 2009 IEEE International
Conference_Location
Baltimore, MD
Print_ISBN
978-1-4244-5639-0
Electronic_ISBN
978-1-4244-5640-6
Type
conf
DOI
10.1109/IEDM.2009.5424286
Filename
5424286
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