DocumentCode :
1651080
Title :
Guaranteeing Performance Yield in High-Level Synthesis
Author :
Hung, W.-L. ; Wu, Xiaoxia ; Xie, Yuan
Author_Institution :
Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA
fYear :
2006
Firstpage :
303
Lastpage :
309
Abstract :
Meeting timing constraint is one of the most important issues for modern design automation tools. This situation is exacerbated with the existence of process variation. Current high-level synthesis tools, performing task scheduling, resource allocation and binding, may result in unexpected performance discrepancy due to the ignorance of the impact of process variation, which requires a shift in the design paradigm, from today´s deterministic design to statistical or probabilistic design. In this paper, we present a variation-aware performance yield-guaranteed high-level synthesis algorithm. The proposed approach integrates high-level synthesis and statistical static timing analysis into a simulated annealing engine to simultaneously explore solution space while meeting design objectives. Our results show that the area reduction is in the average of 14% when 95% performance yield is imposed with the same total completion time constraint
Keywords :
electronic design automation; resource allocation; simulated annealing; statistical analysis; timing; design automation tool; high-level synthesis; resource allocation; simulated annealing; statistical static timing analysis; task scheduling; timing constraint; Algorithm design and analysis; Clocks; Delay effects; High level synthesis; Permission; Resource management; Simulated annealing; Space exploration; Space technology; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer-Aided Design, 2006. ICCAD '06. IEEE/ACM International Conference on
Conference_Location :
San Jose, CA
ISSN :
1092-3152
Print_ISBN :
1-59593-389-1
Electronic_ISBN :
1092-3152
Type :
conf
DOI :
10.1109/ICCAD.2006.320050
Filename :
4110190
Link To Document :
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