Title :
Monolithic three-dimensional integrated circuits using carbon nanotube FETs and interconnects
Author :
Wei, Hai ; Patil, Nishant ; Lin, Albert ; Wong, H. S Philip ; Mitra, Subhasish
Author_Institution :
Dept. of Electr. Eng., Stanford Univ., Stanford, CA, USA
Abstract :
We experimentally demonstrate, for the first time, monolithic three-dimensional integrated circuits consisting of multiple (up to three) layers of monolithically integrated circuits consisting of carbon nanotube field-effect transistors (CNFET) circuits and carbon nanotube (CNT) interconnects. These experimental demonstrations are made possible through a low-temperature (< 250°C) process, presented in this paper, for monolithic three-dimensional integration of CNFETs and CNT interconnects. Such a low-temperature process is enabled by low-temperature wafer-scale transfer of CNTs which decouples high-temperature CNT growth from low-temperature monolithic 3D integration.
Keywords :
carbon nanotubes; cryogenic electronics; field effect transistors; integrated circuit interconnections; monolithic integrated circuits; multilayers; three-dimensional integrated circuits; C; FET; carbon nanotube; field-effect transistors; interconnects; low-temperature wafer-scale transfer; monolithic 3D integrated circuits; multiple layers; CNTFETs; Carbon nanotubes; Contacts; Dielectric substrates; Electric breakdown; Fabrication; Integrated circuit interconnections; Semiconductivity; Silicon; Three-dimensional integrated circuits;
Conference_Titel :
Electron Devices Meeting (IEDM), 2009 IEEE International
Conference_Location :
Baltimore, MD
Print_ISBN :
978-1-4244-5639-0
Electronic_ISBN :
978-1-4244-5640-6
DOI :
10.1109/IEDM.2009.5424292
