• DocumentCode
    1651218
  • Title

    Analog Placement with Symmetry and Other Placement Constraints

  • Author

    Tam, Yiu-Cheong ; Young, Evangeline F Y ; Chu, Chris

  • Author_Institution
    Dept. of Comput. Sci. & Eng., Chinese Univ. of Hong Kong
  • fYear
    2006
  • Firstpage
    349
  • Lastpage
    354
  • Abstract
    In order to handle device matching in analog circuits, some pairs of modules are required to be placed symmetrically. This paper addresses this device-level placement problem for analog circuits and our approach can handle symmetry constraint and other placement constraints simultaneously. The problem of placing devices with symmetry constraint has been extensively studied but none of the previous works has considered symmetry constraint with other placement constraints simultaneously. Instead of handling the constraints by having a penalty term in the cost function to penalize violations, a unified method is proposed that, by adjusting the edge weights in a pair of constraint graphs, can try to satisfy all the placement and symmetry constraints simultaneously in a candidate floorplan solution. The maximum distance of the modules in a symmetry group from the corresponding symmetry axis will be minimized in this weight adjusting step, in order to minimize the total packing area. We have compared our method with the most updated results on this problem (Balasa et al., 2004) when there are only symmetry constraints and results show that our approach can give solutions of better quality, in an acceptable amount of run time. We will also demonstrate the effectiveness of our approach in handling different types of constraints simultaneously by testing on data sets with both symmetry and other placement constraints, and the results are very promising
  • Keywords
    analogue circuits; circuit layout; constraint handling; analog circuits; analog placement; candidate floorplan solution; constraints handling; device matching; Analog circuits; Circuit simulation; Circuit testing; Cost function; Engines; Simulated annealing; Thermal degradation; Upper bound; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer-Aided Design, 2006. ICCAD '06. IEEE/ACM International Conference on
  • Conference_Location
    San Jose, CA
  • ISSN
    1092-3152
  • Print_ISBN
    1-59593-389-1
  • Electronic_ISBN
    1092-3152
  • Type

    conf

  • DOI
    10.1109/ICCAD.2006.320057
  • Filename
    4110197