Title :
A modified Costas loop for clock recovery and frequency synthesis
Author :
Amourah, Mezyad ; Geiger, Randall
Author_Institution :
Dept. of Electr. Eng. & Comput. Eng., Iowa State Univ., Ames, IA, USA
Abstract :
A clock recovery circuit that takes advantage of self biasing, and the presence of delayed and advanced versions of the VCO output to increase the phase detector gain has been designed and simulated using a 0.6 μm CMOS N-well process. This clock recovery circuit shows a fast response time. In addition to clock recovery, this circuit can be used as a frequency multiplier or synthesizer, without additional circuitry. To reduce jitter, the feedback loop is closed only when there is a control signal to adjust the VCO frequency
Keywords :
CMOS digital integrated circuits; circuit feedback; data communication equipment; digital phase locked loops; frequency multipliers; frequency synthesizers; jitter; timing; 0.6 micron; CMOS N-well process; VCO frequency; clock recovery; fast response time; feedback loop; frequency multiplier; frequency synthesis; frequency synthesizer; jitter reduction; modified Costas loop; phase detector gain; self biasing; CMOS process; Circuit simulation; Circuit synthesis; Clocks; Delay; Detectors; Frequency synthesizers; Jitter; Phase detection; Voltage-controlled oscillators;
Conference_Titel :
Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on
Conference_Location :
Monterey, CA
Print_ISBN :
0-7803-4455-3
DOI :
10.1109/ISCAS.1998.704232
