DocumentCode
1651546
Title
Application-specific memory partitioning for joint energy and lifetime optimization
Author
Mahmood, Haroon ; Poncino, Massimo ; Loghi, Mirko ; Macii, YEnrico
Author_Institution
Politec. di Torino, Torino, Italy
fYear
2012
Firstpage
364
Lastpage
369
Abstract
Power management of caches based on turning idle cache lines into a low-energy state is also beneficial for the aging effects caused by Negative Bias Temperature Instability (NBTI), provided that idleness is correctly exploited; unlike energy, aging, being a measure of delay, is in fact a worst-case metric. In this work we propose an application-specific partitioned cache architecture in which a cache is organized as a set of independently addressable sub-blocks; by properly using the idleness of the various banks to drive how the partition is determined, it is possible to extend the effective lifetime of the cache while saving extra energy. Two are the distinctive features of our approach: First, we allow the cache sub-blocks age at different rates, achieving a sort of graceful degradation of performance while extending lifetime beyond the limits of previously published works. Proper architectural arrangements are also introduced in order to cope with the issue of using a progressively smaller cache. Second, the sub-blocks have non-uniform sizes, so to maximally exploit idleness for joint energy and aging optimization. Simulation results show that it is possible to extend the effective lifetime of the cache by more than 2x with respect to previous methods, while concurrently improving energy consumption by about 50%.
Keywords
cache storage; power aware computing; aging optimization; application-specific memory partitioning; application-specific partitioned cache architecture; energy consumption; idle cache line; independently addressable subblock; joint energy optimization; lifetime optimization; negative bias temperature instability; power management; Aging; Clustering algorithms; Computer architecture; Indexing; Measurement; Partitioning algorithms; Random access memory;
fLanguage
English
Publisher
ieee
Conference_Titel
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2012
Conference_Location
Dresden
ISSN
1530-1591
Print_ISBN
978-1-4577-2145-8
Type
conf
DOI
10.1109/DATE.2012.6176498
Filename
6176498
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