DocumentCode
1651781
Title
Parity-Scan Design to Reduce the Cost of Test Application
Author
Fujiwara, Hideo ; Yamamoto, Akihiro
fYear
1992
Firstpage
283
Keywords
Application software; Circuit testing; Clocks; Costs; Design for testability; Flip-flops; Logic testing; Sequential analysis; Sequential circuits; Test pattern generators;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 1992. Proceedings., International
ISSN
1089-3539
Print_ISBN
0-7803-0760-7
Type
conf
DOI
10.1109/TEST.1992.527835
Filename
527835
Link To Document