Title :
Parity-Scan Design to Reduce the Cost of Test Application
Author :
Fujiwara, Hideo ; Yamamoto, Akihiro
Keywords :
Application software; Circuit testing; Clocks; Costs; Design for testability; Flip-flops; Logic testing; Sequential analysis; Sequential circuits; Test pattern generators;
Conference_Titel :
Test Conference, 1992. Proceedings., International
Print_ISBN :
0-7803-0760-7
DOI :
10.1109/TEST.1992.527835
