VLSI implementation of CAVLC decoder with power Optimized for H.264/AVC video decoding

This paper presents an efficient method of the contest-based adaptive variable length code (CAVLC) decoder with power Optimized for H.264/AVC standard. In the proposed design, according to the regularity of the codewords, the first 1 detector is used to solve the problem that the traditional method of table-searching has low efficiency and high power dissipation. Considering the relevance of the data used in the process of RunBeforepsilas decoding, arithmetic operation is combined with FSM, which achieves higher decoding efficiency. According to the CAVLC decoding flow, clock gating is employed in module level and register level respectively, which reduce 43% dynamic power dissipation. The proposed design can decode every syntax element in one clock cycle. When the proposed design is synthesized at clock constraint of 100 MHz, the synthesis result shows that the design costs 11300 gates under a 0.25 um CMOS technology, which meets the demand of real time decoding in H.264/AVC standard.