Co-optimizing process development, layout and circuit design for cost-effective 22nm technology platform

The economic and technological challenges of process development are threatening the timely availability of advanced nodes. Meanwhile design and product organizations are demanding the continued delivery of Moore´s law density scaling to justify node migration. Balancing the requirements of design with the capabilities and physical limitations of advanced processes will require capitalizing on opportunities for co-optimization between process development, layout and circuit design. In this presentation, we will examine the challenges and highlight the opportunities for achieving an economically feasible path to 22 nm.