1652021

Reliability improvement and burn in optimization through the use of die level predictive modeling

Riordan, Walter Carl ; Miller, Russell ; St Pierre, Eric R.

Intel Corp., Chandler, AZ, USA

2005

435

445

circuit optimisation; integrated circuit reliability; integrated circuit yield; semiconductor device reliability; burn in optimization; die level predictive modeling; generic weighting coefficients; infant mortality; latent defects; lot level methods; optimum nearest neighbor effect; predictive defect model; reliability improvement; scrap criteria; wafer level methods; wafer sort yield data; Accelerated aging; Acceleration; Costs; Materials reliability; Nearest neighbor searches; Predictive models; Production; Reliability engineering; Semiconductor device modeling; Thermal stresses;

English

ieee

Reliability Physics Symposium, 2005. Proceedings. 43rd Annual. 2005 IEEE International

0-7803-8803-8

conf

10.1109/RELPHY.2005.1493125

1493125