Title :
Wafer die yield prediction by heuristic methods
Author :
Chen, Kuentai ; Chang, Ping-Yu ; Yeh, Chien-Hsing
Author_Institution :
Dept. of Ind. Eng. & Manage., Mingchi Univ. of Technol., Taishan, Taiwan
Abstract :
Yield is a very important criterion to measure the semiconductor wafer fabrication facilities (FABs) productivity. The finished products will be check by Wafer Acceptance Test (WAT) and Circuit Probe (CP) to classified into ferior goods or inferior goods. This research applied the data from WAT and CP for the selection of the most important measuring parameters to improve the yield. Three methods, namely Support Vector Regression (SVR), Group Method of Data Handling (GMDH), Genetic Algorithm-Backpropagation Neural Network (GA-BPNN), were applied to model the system and were compared to investigate the best variable combination among 164 variables. It was found that the data need to be first classified in order to enhance the performances. Also, GA-BPNN out performed other methods using only 9 variables. The results were confirmed by engineers and used in FABs to improve the yield by controlling these parameters.
Keywords :
backpropagation; electronic engineering computing; genetic algorithms; identification; integrated circuit testing; integrated circuit yield; neural nets; regression analysis; support vector machines; backpropagation neural network; circuit probe; genetic algorithm; group method of data handling; heuristic method; semiconductor wafer fabrication facilities; support vector regression; wafer acceptance test; wafer die yield prediction; Adaptation model; Analytical models; Artificial neural networks; Input variables; Integrated circuit modeling; Predictive models; Productivity; genetic algorithms; neural networks; support vector regression; wafer acceptance test; yield prediction;
Conference_Titel :
Computers and Industrial Engineering (CIE), 2010 40th International Conference on
Conference_Location :
Awaji
Print_ISBN :
978-1-4244-7295-6
DOI :
10.1109/ICCIE.2010.5668273
