Title :
Design challenges for 22nm CMOS and beyond
Author_Institution :
Intel Corp., Hillsboro, OR, USA
Abstract :
This paper presents technology and economic challenges posed by 22 nm CMOS and beyond. They can be addressed by advances in design technology, methodology, validation, and testing, to continue to enjoy the benefits of CMOS scaling in the future, as we have over the past decades.
Keywords :
CMOS integrated circuits; electronic design automation; integrated circuit design; CMOS scaling; automated design methodology; economic challenges; integrated circuit design; size 22 nm; CMOS technology; Cost function; Degradation; Design methodology; Design optimization; Hardware; Manufacturing; Paper technology; Power generation economics; Testing;
Conference_Titel :
Electron Devices Meeting (IEDM), 2009 IEEE International
Conference_Location :
Baltimore, MD
Print_ISBN :
978-1-4244-5639-0
Electronic_ISBN :
978-1-4244-5640-6
DOI :
10.1109/IEDM.2009.5424329
