An Electrothermally-Aware Full-Chip Substrate Temperature Gradient Evaluation Methodology for Leakage Dominant Technologies with Implications for Power Estimation and Hot-Spot Management

As CMOS technology scales into the nanometer regime, power dissipation and associated thermal concerns in high-performance ICs due to on-chip hot-spots and thermal gradients are beginning to impact VLSI design. Moreover, elevated substrate (junction or die) temperature strongly influences IC performance, reliability, and packaging/cooling cost. Hence, accurate estimation of substrate thermal profiles is critical. This paper presents an accurate chip-level electrothermally-aware methodology for spatial silicon substrate temperature estimation. The methodology self-consistently incorporates various electrothermal couplings arising mainly due to the strong dependence of subthreshold leakage on temperature and also employs an accurate package thermal model, to account for inhomogeneous layers and non-cubic structure, which are not considered in traditional methods. The proposed methodology becomes increasingly effective as technology scales due to increasing leakage. Furthermore, it is shown that considering realistic package thermal models not only improves the accuracy of estimating temperature distribution but also has significant implications for power estimation and hot-spot management