An efficient algorithm for a memory-based systolic array VLSI implementation of type IV DCT

A new VLSI algorithm for a high throughput memory-based systolic array implementation for a prime length type IV discrete cosine transform based on parallel cycle convolution structures is presented. It uses a new restructuring input sequence for a parallel restructuring of type IV DCT into cycle convolution structures as basic computational forms. The proposed algorithm can be mapped onto two linear systolic arrays that can be merged into a single linear systolic array using an appropriate hardware sharing technique. A highly efficient hardware accelerator can be thus obtained using the proposed algorithm that has modular and regular structure with a good architectural topology that allow an efficient VLSI implementation. Moreover, the proposed VLSI has a high processing speed, and a low hardware complexity and I/O costs.