1652267

New approach of 90nm low-k interconnect evaluation using a voltage ramp dielectric breakdown (VRDB) test

Aubel, Oliver ; Kiene, Michael ; Yao, Walter

AMD Saxony, Germany

2005

483

489

Poole-Frenkel effect; dielectric measurement; electric breakdown; extrapolation; integrated circuit interconnections; integrated circuit measurement; integrated circuit modelling; integrated circuit reliability; 90 nm; BEoL-TDDB test; BTS; Poole-Frenkel equation; VRDB test; bias temperature stress test; breakdown voltage distribution extrapolation model; diffusion driven effects; failure mechanisms; gate-oxide-like failures; low temperature dependence; low-k interconnect; minimum space dielectric areas; product lifetime prediction; reliability; time dependant dielectric breakdown; voltage acceleration; voltage ramp dielectric breakdown test; Breakdown voltage; Copper; Dielectric breakdown; Dielectric materials; Dielectric measurements; Electric breakdown; Integrated circuit interconnections; Stress; Temperature measurement; Testing;

English

ieee

Reliability Physics Symposium, 2005. Proceedings. 43rd Annual. 2005 IEEE International

0-7803-8803-8

conf

10.1109/RELPHY.2005.1493133

1493133