Impact of strain engineering and channel orientation on the ESD performance of nanometer scale CMOS devices

This paper provides the first detailed insight into the effect of strain engineering on ESD performance of nano-scale ggNMOS and ggPMOS protection devices by coupling electro-thermal simulations with tight-binding bandstructure calculation, mobility modeling and thermal conductivity evaluation. The analysis reveals that apart from mobility enhancement, in the ESD domain, strain engineering plays a more promising role than that in normal device application due to bandgap engineering and minority-carrier mobility modulation. The preferential stress and channel orientations for both ggNMOS and ggPMOS are also proposed for the first time. Moreover, it is shown that while strain induced thermal properties deteriorate at high-level stress (5 GPa), the ESD optimization space at such high-level stress can be extended beyond the mobility enhancement saturation region because of the positive feedback from bandgap narrowing. Finally, it is shown that the benefit of strain engineering on ESD performance improves even further with scaling.