DocumentCode
1652366
Title
Design and Integration Methods for a Multi-threaded Dual Core 65nm Xeon® Processor
Author
Varada, Raj ; Sriram, Mysore ; Chou, Kris ; Guzzo, James
Author_Institution
Intel Corp., Santa Clara, CA
fYear
2006
Firstpage
607
Lastpage
610
Abstract
The success of building a complex multi-billion transistor processor is very dependent on robust and silicon proven design and integration methods. The complexity of 65nm process and striving for best in class performance with aggressive time to market schedule put a heavy emphasis on innovative design and integration methods to enable working silicon. In this paper, we describe the design and integration methods successfully used in a multi-threaded dual core 65nm Xeonreg Processor
Keywords
microprocessor chips; multi-threading; 65 nm; innovative design; integration method; multithreaded dual core 65nm Xeon processor; transistor processor; Buildings; Delay; Design methodology; Logic; Permission; Power dissipation; Robustness; Silicon; Time to market; Yarn; Design Methods; Integration; Xeon®; processor;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer-Aided Design, 2006. ICCAD '06. IEEE/ACM International Conference on
Conference_Location
San Jose, CA
ISSN
1092-3152
Print_ISBN
1-59593-389-1
Electronic_ISBN
1092-3152
Type
conf
DOI
10.1109/ICCAD.2006.320023
Filename
4110239
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