DocumentCode :
1652438
Title :
Influence of process parameters and bump geometry on the residual stress distribution in a chip-on-foil bonding process
Author :
Suter, P. ; Bauknecht, R. ; Graf, T. ; Duran, H. ; Venter, I.
Author_Institution :
Inst. of Electron., HTA Luzern, Horw, Switzerland
fYear :
2005
Firstpage :
513
Lastpage :
517
Keywords :
chip scale packaging; chip-on-board packaging; elastic deformation; finite element analysis; internal stresses; lead bonding; optimisation; plastic deformation; FEM; bump arrangement; bump geometry; chip-on-foil bonding process; corner bump failures; display driver circuits; elasto-plastic deformation; failure rate reduction; finite-element simulation; foil induced shear forces; inner-lead bonding; optimization; process parameter effects; residual stress distribution; shear stress reduction; Assembly; Bonding processes; Displays; Driver circuits; Geometry; Gold; Lead; Residual stresses; Temperature; Thermal stresses;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Reliability Physics Symposium, 2005. Proceedings. 43rd Annual. 2005 IEEE International
Print_ISBN :
0-7803-8803-8
Type :
conf
DOI :
10.1109/RELPHY.2005.1493138
Filename :
1493138
Link To Document :
بازگشت