Sorting methods used in parallel turbo decoding for LTE systems

This paper presents the main methods used for sorting when parallel decoding architecture is used for Long Term Evolution (LTE) systems turbo codes. Usually, the parallelization factor N represents the number of required interleavers. We propose a decoding architecture with only one Quadratic Permutation Polynomial (QPP) interleaver. All the interleaved addresses are placed on the same memory location, as a consequence of QPP interleaver algebraic properties, but sorting is needed before sending the correct data to each decoder unit. The sorting methods are compared in order to find the most suitable one for Field Programmable Gate Array (FPGA) implementation. Even-odd merge sorting method is selected, and the obtained results are provided in terms of occupied resources and maximum speed.