VLSI implementation-oriented (3, k)-regular low-density parity-check codes

In the past few years, Gallager´s low-density parity-check (LDPC) codes received a lot of attention and many efforts have been devoted to analyzing and improving their error-correcting performance. However, little consideration has been given to the LDPC decoder VLSI implementation. The straightforward fully parallel decoder architecture usually incurs too high complexity for many practical purposes and should be transformed to a partly parallel realization. Unfortunately, due to the randomness of LDPC codes, it is nearly impossible to develop an effective transformation for an arbitrarily given LDPC code. We propose a joint code and decoder design approach to construct a class of (3, k)-regular LDPC codes which exactly fit a partly parallel decoder implementation and have a very good performance. Moreover, for such LDPC codes, we propose a systematic, efficient encoding scheme by effectively exploiting the sparseness of its parity check matrix