Title :
Design of new DSP instructions and their hardware architecture for high-speed FFT
Author :
Sung Lee, Jae ; Seop Jeon, Young ; Sunwoo, Myung H.
Author_Institution :
Sch. of Electron. Eng., Ajou Univ., Suwon, South Korea
fDate :
6/23/1905 12:00:00 AM
Abstract :
This paper presents new DSP (digital signal processor) instructions and their hardware architecture for high-speed FFT. The instructions perform new operation flows, which are different from the MAC (multiply and accumulate) operation on which existing DSP chips heavily depend. The paper proposes a DPU (data processing unit) supporting the instructions and shows two times faster than existing DSP chips for FFT. The architecture has been modeled by the Verilog HDL and logic synthesis has been performed using the 0.35 μm standard cell library. The maximum operating clock frequency is about 144.5 MHz and the architecture will be employed on an application-specific DSP chip
Keywords :
application specific integrated circuits; digital arithmetic; digital signal processing chips; fast Fourier transforms; hardware description languages; modulation; telecommunication computing; 0.35 micron; ASIC; DMT modulation; DSP instructions; OFDM; Verilog HDL; application specific DSP chips; data processing unit; digital signal processor; discrete multi-tone modulation; hardware architecture; high-speed FFT; logic synthesis; multiply and accumulate operation; operating clock frequency; orthogonal frequency division multiplexing; Application specific integrated circuits; Arithmetic; Clocks; Computer architecture; Digital signal processing; Digital signal processing chips; Equations; Hardware design languages; Multiaccess communication; OFDM modulation;
Conference_Titel :
Signal Processing Systems, 2001 IEEE Workshop on
Conference_Location :
Antwerp
Print_ISBN :
0-7803-7145-3
DOI :
10.1109/SIPS.2001.957333