DocumentCode
1652650
Title
Carbon Nanotube Transistor Circuits - Models and Tools for Design and Performance Optimization
Author
Wong, H. S Philip ; Deng, Jie ; Arash, Arash ; Hazeghi, Hazeghi ; Krishnamohan, Tejas ; Wan, Gordon C.
Author_Institution
Center for Integrated Syst., Stanford Univ., CA
fYear
2006
Firstpage
651
Lastpage
654
Abstract
In this paper, we describe the development of device models and tools for the design of new transistors such as the carbon nanotube transistor. An HSPICE model for enhancement mode nanotube transistor has been developed. It can be used for design of nanotube transistor circuits as well as to study performance benefits of the new transistor. A model of the carbon nanotube transistor with Schottky barrier is presented. The model enables device design and performance optimization
Keywords
SPICE; Schottky barriers; carbon nanotubes; logic CAD; nanotube devices; transistor circuits; HSPICE model; Schottky barrier; carbon nanotube transistor circuits; performance optimization; transistor design; Carbon nanotubes; Chemicals; Circuits; Contact resistance; Immune system; Inductance; Nanobioscience; Optimization; Schottky barriers; Semiconductor process modeling;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer-Aided Design, 2006. ICCAD '06. IEEE/ACM International Conference on
Conference_Location
San Jose, CA
ISSN
1092-3152
Print_ISBN
1-59593-389-1
Electronic_ISBN
1092-3152
Type
conf
DOI
10.1109/ICCAD.2006.320031
Filename
4110247
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