Author :
Katti, G. ; Mercha, A. ; Van Olmen, J. ; Huyghebaert, C. ; Jourdain, A. ; Stucchi, M. ; Rakowski, M. ; Debusschere, I. ; Soussan, P. ; Dehaene, W. ; De Meyer, K. ; Travaly, Y. ; Beyne, E. ; Biesemans, S. ; Swinnen, B.
Abstract :
In this paper we demonstrate functional 3D circuits obtained by a 3D Stacked IC approach using both Cu Through Silicon Vias (TSV) First and cost effective solution Die-to-Wafer Hybrid Collective bonding. The Cu TSV-First process is inserted between contact and M1. The top die is thinned down to 25 ¿m and bonded to the landing wafer by Hybrid Bonding. Measurements and simulations of the power delay trade-offs of various 3D Ring Oscillator are provided as a demonstration of the relevance of such process route and of the design/simulation capabilities.
Keywords :
copper; integrated circuit interconnections; oscillators; three-dimensional integrated circuits; wafer bonding; 3D ring oscillator; 3D stacked IC; Cu; TSV; die-to-wafer hybrid collective bonding; power delay trade-offs; size 25 mum; through silicon vias; Atherosclerosis; Cost function; Degradation; Delay; Integrated circuit interconnections; Silicon; Three-dimensional integrated circuits; Through-silicon vias; Very large scale integration; Wafer bonding;
